1. Field of the Invention
The present invention is generally related to the field of DRAM architecture, and, more particularly, to a 6 F2 DRAM architecture with a 3 F-pitch folded digitline sense amplifier.
2. Description of the Related Art
Memory devices are typically provided as internal storage areas in the computer. There are several different types of memory. One type of memory is random access memory (RAM) that is typically used as main memory in a computer environment. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents.
A dynamic random access memory (DRAM) is made up of memory cells. Each cell of a modern DRAM includes a transistor and a capacitor, where the capacitor holds the value of each cell, namely a “1” or a “0”, as a charge on the capacitor. Because the charge on a capacitor gradually leaks away, DRAM capacitors must be refreshed on a regular basis. A memory device incorporating a DRAM memory includes logic to refresh (recharge) the capacitors of the cells periodically or the information will be lost. Reading the stored data in a cell and then writing the data back into the cell at a predefined voltage level refreshes a cell. The required refreshing operation is what makes DRAM memory dynamic rather than static.
Referring to FIG. 1, a schematic diagram of an illustrative DRAM memory cell 10 is depicted. The cell 10 is illustrated as having a capacitor 12 and an access transistor 14. The capacitor 12 is used to store a charge. The charge represents a bit of information. The access transistor 14 acts as a switch for the capacitor 12. That is, the access transistor 14 controls when a charge is placed on the capacitor 12, and when a charge is discharged from the capacitor 12. A word line 16 is coupled to a control gate of the access transistor 14. When a cell is read, the word line 16 activates the control gate of the transistor 14. Once this happens, any charge (or lack of charge) stored on the capacitor 12 is shared with a conductive digitline 18 coupled to the drain of the access transistor 14. This charge is then detected in the digitline 18 by a sense amplifier (not shown) and then processed to determine the bit state of the cell 10. Tiling a selected quantity of cells 10 together, such that the cells 10 along a given digitline 18 do not share a common word line 16 and the cells 10 along a common word line 16 do not share a common digitline 18, forms a memory array. A typical memory array contains thousands or millions of cells 10.
FIGS. 2A and 2B are, respectively, a plan view and a schematic drawing of an illustrative DRAM cell with a folded bit line architecture. As depicted in FIG. 2A, DRAM memory cells 10 are constructed in pairs, to allow sharing of the digitline contact 22. A dashed line 24 is drawn around a single illustrative memory cell 10. Sharing the digitline contact 22 significantly reduces overall cell size. The memory cell pairs consist of an active area rectangle 26 (in this case N+active area), a pair of metal or polysilicon word lines 16, a single digitline contact 22, a metal or polysilicon digitline 18, and a pair of cell capacitors 12 formed with, for example, oxide-nitride-oxide (O—N—O) dielectric between two layers of polysilicon. Of course, cell dielectric other than O—N—O combinations may be employed, and the cell plates may be formed of a variety of conductive materials, e.g., a metal. For some processes, the word line polysilicon is silicided to reduce the sheet resistance, permitting longer word line segments without reducing speed. The memory cell layout, shown in FIG. 2A, is essentially under the control of process engineers, since every aspect of the memory bit must meet stringent performance criteria.
The single memory cell 10 shown within the dashed line box 24 in FIG. 2A is by definition an eight square feature (8 F2) cell. The intended definition of feature is minimum realizable process dimension, but in actual fact equates to a dimension that is half of the word line (row) or digitline (column) pitch. A 0.25 μm process having word line and digitline pitches of 0.6 μm yields a memory bit size that is 8×(0.3 μm)2=0.72 μm2. Explanation of the 8 F2 designation is easier with the aid of FIG. 2A. The imaginary box 24 drawn around the memory cell 10 defines the cell's outer boundary. Along the x-axis, the box 24 includes ½ of the digitline contact 22 feature (½ F), 1 word line 16 feature (1 F), 1 capacitor 18 feature (1 F), 1 field oxide feature (1 F), and ½ poly space feature (½ F), which totals to 4 features. Along the y-axis, this box 24 contains two ½ field oxide features and 1 active area 26 feature, which totals to 2 features. The area of the single memory cell 10 is, as defined herein, 4 F×2 F=8 F2.
The memory cell array depicted in FIG. 2A has a folded array architecture. This results from the fact that each word line 16 connects (forms a crosspoint) with a memory transistor on every other digitline 18 and must pass around memory transistors as field poly on the remaining digitlines 18. The field poly in each memory cell 10 adds two square features to what would have been a 6 F2 cell otherwise. Although the folded array yields a cell that is 25% larger than other array architectures, it also produces superior signal-to-noise performance, especially when combined with some form of digitline twisting. Superior low noise performance made folded array architecture the architecture of choice since the 64 kbit generation.
FIG. 2B is a schematic depiction of the illustrative memory cell array depicted in FIG. 2A with a folded digitline architecture. As shown therein, the sense amplifier 30 reads digitlines 18 (D and D*) from the same sub-array (sub-array #1). Using such a construction, all of the noise sources affecting the sense amplifier 30 will have many common nodes that substantially cancel one another. Thus, with folded line architecture, the digitlines 18 are more likely to remain substantially unaffected by external noises and sensing of the difference between D (the sensed line) and D*(the reference line) is easier for the sense amplifier 30.
An alternative to the folded array architecture is the open digitline architecture, popular prior to the 64 kbit generation. FIGS. 3A-3B are, respectively, a plan view and a schematic depiction of such an open digitline architecture. Seen schematically in FIG. 3B, this open digitline architecture also features a sense amplifier 30, but it is positioned between two separate sub-arrays (sub-array #1, sub-array #2). Unlike the folded digitline architecture shown in FIG. 2B, true and complement digitlines 18 (D and D*) connected to each sense amplifier pair come from separate arrays. This precludes the use of digitline twisting to improve signal-to-noise performance and is one reason why the industry has, in general, switched to the folded digitline architecture. Also note that, unlike the folded digitline architecture, each word line 16 in an open digitline architecture connects to memory transistors on every digitline 18—crosspoint style arrays. See FIG. 3A. This feature permits a 25% reduction in memory bit size to only 6 F2 since the word lines 16 do not have to pass alternate memory cells 10 as field poly. Unfortunately, most manufacturers have found that the signal-to-noise problems of open digitline architecture outweigh the benefits derived from reduced array size. The layout for an array of standard 6 F2 memory cell pairs is shown in FIG. 3A. A dashed box 28 is drawn around one of the memory cells 10 to show the 6 F2 cell boundary. Again, two memory cells share a common digitline contact 22 to improve layout efficiency. Along the x-axis, the box 28 includes ½ of the digitline contact 22, one word line 16 feature, one capacitor 12 feature, and ½ of a field oxide feature, for a total of 3 features. Along the y-axis, the box 28 includes two ½ field oxide features and one active area 26 feature, for a total of 2 features. The area of the single memory cell shown in FIG. 3A is 3 F×2 F=6 F2.
A thorough understanding of both folded and open digitline architectures by those skilled in the art assists in appreciating the characteristics and benefits of the present invention. The open digitline and folded digitline architectures both have distinct advantages and disadvantages. While open digitline architectures achieve smaller array layouts by virtue of using smaller 6 F2 memory cells, they also suffer from poor noise performance. A relaxed word line pitch which stems from the 6 F2 memory cell simplifies the task of word line driver layout. Sense amplifier layout, though, is difficult because the array configuration is inherently half pitch—one sense amplifier for every two digitlines. Folded digitline architectures, on the other hand, have superior signal-to-noise, at the expense of larger, less efficient array layout. Good signal-to-noise performance stems from the adjacency of true and complement digitlines and the capability to twist these digitline pairs. Sense amplifier layout in the folded digitline architecture is simplified because the array configuration is quarter pitch—one sense amplifier for every four digitlines. Word line driver layout is more difficult since the word line pitch is effectively reduced in folded architectures.
The present invention is directed to a device and various methods that may solve, or at least reduce, some or all of the aforementioned problems.